These logical analyser in the LAP-F1 series are multi-purpose and PC-based logic analysers, which offer high sample rate, large amount of channels and a deep channel count in a single instrument.
All the LAP-F1 series logical analysers run on windows 32 and 64 bit versions. Furthermore, the hardware inside this analyser features a Xilinx high-performance FPGA chip and exclusive active probes that enhance sampling accuracy and stability. The extensive protocol library consists of at least 110 protocol decoders. All devices can be expanded with optional features like direct data streaming to a computer, channel folding and eMMC decoding capability. Moreover, a USB 3.0 connection is available for fast data transfer.
The LAP-F1 series software user interface is similar to the LAP-C series interface as it also allows for easy debugging, but comes in a black, modern look. All functions are accessed from the main menu and it is also possible to enter favourite functions directly from the customizable direct access icon bar. The familiar channel and trigger settings occupy the left part of the screen estate, while to the right a control panel facilitates access to the most common acquisition settings. The lower part of the screen gives access to the auxiliary analysis windows. An image of the user interface is shown below.
The models in the LAP-F1 series differ mainly in memory depth and channels. Below is a convenient overview of the differences between all the models.
Model | Channels | Memory depth [Mbit] | Price |
---|---|---|---|
LAP-F1404M | 40 | 4 | |
LAP-F1408M | 40 | 8 | |
LAP-F14016M | 40 | 16 | |
LAP-F14032M | 40 | 32 | |
LAP-F14064M | 40 | 64 | |
LAP-F1644M | 64 | 4 | |
LAP-F1648M | 64 | 8 | |
LAP-F16416M | 64 | 16 | |
LAP-F16432M | 64 | 32 | |
LAP-F16464M | 64 | 64 |
Bandwidth | 200 MHz |
Vertical resolution | 12 Bits, 2.44 mV/step |
Input impedance | 190 to 500 kΩ (±10%) |
Input capacitance | 4.3 to 8.2 pF (± 2pF) |
Operating system | Windows 8.1 and 7 32 and 64 bit |
Connectivity | USB 3.0 (preferred), USB 2.0 (compatible) |
Dimensions | 322 x 180 x 38 mm |
Weight | ~2 kg |
For more information please refer to the manual and the datasheet.
LAP-F1 series models contain a lot of software functions and this table shows some of the most important software functions.
Add bars | Auto save | Auto run | Automatic updates |
DSO connection | Files compression | File Export | General software description |
Multiple languages | Memory view | Navigator | Packet list |
Pre/post triggering | Protocol decoders (>110) | Protocol Triggers (HW) | Real-time signal activity |
State list and waveform view | Statistics | Trace information | Trigger delay |
Trigger events | Trigger in/out | Trigger Mark | Trigger pass counter |
Trigger sequence level | Trigger Voltage | Waveform and UI customization | Zooming and panning |
More information about these functions or other functions can be found on the Zeroplus software webpage.
More information about the different protocol decoders can be found on the Zeroplus protocol decoders webpage.
Software functions of the LAP-F1 series can be downloaded from the Zeroplus software download web-page.
What the logic analysers in the LAP-F1 series come bundled with depends on their amount of channels. In the table below all contents of the package are listed.
Channels | 40 | 64 |
CD with driver, software and manual | 1 | 1 |
eMMC probes | 4 | 4 |
eMMC Clock In probe | 1 | 1 |
USB 3.0 cable (A-A type 32.5 cm) | 25 | 37 |
Signal/Ground cable pair | 40 | 64 |
Clip-on connector | 80 | 128 |
USB 3.0 cable PC-LAP F1 | 1 | 1 |
BNC cable | 1 | 1 |
Power cord | 1 | 1 |
Power cable | 1 | 1 |
All options with blue text offer a clickable link to the product. These options can be bundled with the device or ordered at a later point.
Channel Folding | The LAP-F1 offers the ability to concentrate the available memory on a limited number of channels. For example when only 32 of the 64 channels are in use, the 4 Mbit memory per channel can be combined into 8 Mbit for each channel. Enable only 16 channels for 16 Mb/ch, only 8 channels for 32 Mb/ch, etc.. |
eMMC5.1/SD3.0 | With special eMMC probes and 32 channel 2 GHz sampling the eMMC protocol can be fully triggered and decoded. As eMMC only has 11 signals the remaining channels can be used for other high speed acquisition. |
Long time record | With the long time acquisition option the device can stream directly to a computer, which allows for storage of long sequences of data. This is useful in burn-in in tests or long term testing. It offers up to 7 hours or up to a month of record time depending on the sampling settings. |
Standard probes | The default probes that are bundled with the device. |
Low Voltage probes | These active probes are designed for low voltage signals. |
Negative logic probes | The Negative logic probes are specially designed for negative logic signals. |
eMMC probes | The eMMC probes are specially designed for eMMC acquisitions. They can also be used for SD signal sampling. |
LAP-F User Guide |
(5.87 MB) | Download |